1. Technical Field
The present invention relates to a tri-state bus controller for an integrated circuit and, more particularly, to a tri-state controller that eliminates contention between various drivers for the bus and completes driver changeover during a single clock cycle.
2. Description of the Prior Art
A classic challenge in ASIC design is the management of internal bidirectional or multi-party tri-state buses. In particular, a problem arises with changeover of "bus mastership" without contention ("contention" being defined as more than one set of drivers momentarily driving the bus). Bus contention, even for a short duration, can result in excessive power dissipation and, ultimately, reduced product reliability. ASICs are more susceptible to this problem than custom integrated circuits since automatic placement and routing tools do not conventionally consider the issue of balancing delays along multiple paths--such delays being a source of bus mastership contention. To minimize contention, one would need to carefully balance the delay paths to the multiple groups of tri-state drivers that are scattered across the integrated circuit. In instances with a large number of drivers and/or a large integrated circuit die size, this "brute force" technique becomes extremely tedious, expensive and time-consuming. Indeed, this solution becomes even more intractable in arrangements that exhibit asymmetric enable/disable times for tri-state drivers (a common occurrence), or even dissimilar driver types sharing the same bus.
An alternative solution to controlling bus mastership is to change bus masters across two clock cycles. In the first cycle, all of the masters are disconnected from the bus (i.e., each master is "disabled"). In the second clock cycle, a new master (and only one master) assumes control of the bus. The use of two clock cycles thus guarantees that no two masters will be simultaneously enabled, a significant advantage over other prior solutions. However, in high performance systems, it can be a distinct disadvantage to consume two clock cycles to changeover bus mastership.
An exemplary "single clock" prior art solution includes a gating control arrangement associated with each "bus enable" signal, the arrangement requiring that all other "bus enables" be de-asserted before a new "bus enable" can be asserted. It has been found, however, that the gating arrangement is prone to glitching behavior related to recognizing "de-assertion" and, like the "brute force" technique, requires some attention during placement and routing. Further, the gating control arrangement scales poorly as the number of bus masters grows, since each driver circuit must be fully interconnected to every other driver circuit on the bus.
Thus, a need remains in the art for a tri-state bus controller that consumes only a single clock cycle, yet eliminates the bus contention problem prevalent in conventional circuit design.